1. Field of the Invention
The present invention relates to design for a semiconductor integrated circuit. More particularly, the present invention relates to an apparatus, a method and a program for designing the semiconductor integrated circuit, which are used in a process of designing a wire layout between logic cells.
2. Description of the Related Art
In a layout design process for a system LSI, which is an important process in the entire design thereof, an arrangement of logic gates and automatic routing are executed by use of wire/connection information acquired by logic design and by use of a logic cell library prepared by circuit design. In this case, it is required to minimize a chip area.
As an integrated circuit has become larger in scale in recent years, necessary information involved in the circuit design has been increased more and more. A process time in each step and memory usage of a design apparatus used in the layout design process, which is a so-called CAD tool, tend to be increased.
In the case of executing automatic routing design for the LSI in the conventional layout design process, there has been employed: 1) a method for routing the entire chip all at one time; or 2) a hierarchical layout method, in which respective logic modules are implemented as hard macro, the modules implemented as hardware are arranged on a chip, and the modules implemented as hardware are mutually wired.
However, with regard to 1) the method for routing the entire chip all at one time, an increase of the memory usage and an increase of the process time are inevitable because the wire/connection information concerning the entire chip is dealt simultaneously. Accordingly, when the integrated circuit becomes large in scale, there also occur a possibility that the layout may be disabled by out-of-memory and a possibility that a design period may be prolonged.
Meanwhile, with regard to 2) the hierarchical layout method, such a problem of the memory usage is solved, which is inherent in the case of the routing executed all at one time, because limitations can be put on memory usage to be required. However, a degree of flexibility in routing is restricted because a region of the logic module is set as a routing forbidden area, resulting in an increase of the chip area. In addition, since each module is dealt independently of the others, it is difficult to overcome, at the design step, timing constraints on routing for the modules and process antenna constraints caused by an influence of charges accumulated between respective wire layers, which are generated in a device fabrication process. As a consequence, the design period for the chip tends to be prolonged.